Configuration of Vivado 2014.4 BRAM, adder/accumulator and DDS IP blocks
necessary to build the Kiwi Verilog code.
    Updated 6 Apr 2018

In Vivado:
    In the Project Manager > Sources window select the "IP Sources" tab at the bottom.
    Open the IP folder and double-click on an IP block to get the "Re-customize IP" window.
    Make your changes and then generate (re-compile) the new IP.

    Below are the settings used for each IP block.

Block Memory Generator (8.2):

used by rx/receiver.v:
    Component Name
        ipcore_bram_8k_16b
	Basic
		Interface Type
			> native
		Memory Type
			> simple dual port RAM
		Common Clock
		    > no
		Algorithm
			minimum area
	Port A Options
		Width
			> 16
		Depth
			> 8192
		Operating Mode
			> no change
		Enable Port Type
			> always enabled
	Port B Options
		Width
			> 16
		Enable Port Type
			> always enabled
		> no output registers
	Other Options
	    > none
	Summary (if anything here is different you configured something incorrectly)
		#18k:0 #36k:4 B-latency:1 addr-A-width:13 addr-B-width:13

used by rx/iq_sampler_8k_32b.v:
    Component Name
        ipcore_bram_8k_32b
	Basic
		Interface Type
			> native
		Memory Type
			> simple dual port RAM
		Common Clock
		    > no
		Algorithm
			minimum area
	Port A Options
		Width
			> 32
		Depth
			> 8192
		Operating Mode
			> no change
		Enable Port Type
			> always enabled
	Port B Options
		Width
			> 32
		Enable Port Type
			> always enabled
		> no output registers
	Other Options
	    > none
	Summary (if anything here is different you configured something incorrectly)
		#18k:1 #36k:7 B-latency:1 addr-A-width:13 addr-B-width:13

used by gps/sampler.v:
    Component Name
        ipcore_bram_gps_16k_1b_4k_4b
	Basic
		Interface Type
			> native
		Memory Type
			> simple dual port RAM
		Common Clock
		    > no
		Algorithm
			minimum area
	Port A Options
		Width
			> 1
		Depth
			> 16384
		Operating Mode
			> no change
		Enable Port Type
			> always enabled
	Port B Options
		Width
			> 4
		Enable Port Type
			> always enabled
		> no output registers
	Other Options
	    > none
	Summary (if anything here is different you configured something incorrectly)
		#18k:1 #36k:0 B-latency:1 addr-A-width:14 addr-B-width:12

used by gps/logger.v:
    Component Name
        ipcore_bram_1k_16b
	Basic
		Interface Type
			> native
		Memory Type
			> simple dual port RAM
		Common Clock
		    > no
		Algorithm
			minimum area
	Port A Options
		Width
			> 16
		Depth
			> 1024
		Operating Mode
			> no change
		Enable Port Type
			> always enabled
	Port B Options
		Width
			> 16
		Enable Port Type
			> always enabled
		> no output registers
	Other Options
	    > none
	Summary (if anything here is different you configured something incorrectly)
		#18k:1 #36k:0 B-latency:1 addr-A-width:10 addr-B-width:10

used by gps/e1bcode.v:
    Component Name
        ipcore_bram_256_16b_4k_1b
	Basic
		Interface Type
			> native
		Memory Type
			> simple dual port RAM
		Common Clock
		    > no
		Algorithm
			minimum area
	Port A Options
		Width
			> 16
		Depth
			> 256
		Operating Mode
			> no change
		Enable Port Type
			> always enabled
	Port B Options
		Width
			> 1
		Enable Port Type
			> always enabled
		> no output registers
	Other Options
	    > none
	Summary (if anything here is different you configured something incorrectly)
		#18k:1 #36k:0 B-latency:1 addr-A-width:8 addr-B-width:12

used by cpu.v:
    Component Name
        ipcore_bram_cpu_2k_16b
	Basic
		Interface Type
			> native
		Memory Type
			> true dual port RAM
		Common Clock
		    > no
		Algorithm
			minimum area
	Port A Options
		Write Width
		    > 16
		Read Width
			> 16
		Write Depth
			> 2048
		Read Depth
			(2048)
		Operating Mode
			> write first
		Enable Port Type
			> use ENA pin       <=== NOTE! ***
		Port A Output Reset Options
			RSTA pin
			    > yes           <=== NOTE! ***
		    Output Reset Value (Hex)
		        > 8000
		> no output registers
	Port B Options
		Write Width
		    > 16
		Read Width
			> 16
		Write Depth
			(2048)
		Read Depth
			(2048)
		Operating Mode
			> write first
		Enable Port Type
			> use ENB pin       <=== NOTE! ***
		> no output registers
	Other Options
	    Memory Initialization
	        Fill Remaining Memory Locations
	            > 8000 (hex)        <=== NOTE! ***
	Summary (if anything here is different you configured something incorrectly)
		#18k:0 #36k:1 A-latency:1 B-latency:1 addr-A-width:11 addr-B-width:11

used by cpu.v:
    Component Name
        ipcore_bram_512_32b
	Basic
		Interface Type
			> native
		Memory Type
			> true dual port RAM
		Common Clock
		    > no
		Algorithm
			minimum area
	Port A Options
		Write Width
		    > 32
		Read Width
			> 32
		Write Depth
			> 512
		Read Depth
			(512)
		Operating Mode
			> write first
		Enable Port Type
			> use ENA pin       <=== NOTE! ***
		> no output registers
	Port B Options
		Write Width
		    > 32
		Read Width
			> 32
		Write Depth
			(512)
		Read Depth
			(512)
		Operating Mode
			> write first
		Enable Port Type
			> use ENB pin       <=== NOTE! ***
		> no output registers
	Other Options
	    > none
	Summary (if anything here is different you configured something incorrectly)
		#18k:0 #36k:1 A-latency:1 B-latency:1 addr-A-width:9 addr-B-width:9

used by host.v:
    Component Name
        ipcore_bram_16k_1b_1k_16b
	Basic
		Interface Type
			> native
		Memory Type
			> true dual port RAM
		Common Clock
		    > no
		Algorithm
			minimum area
	Port A Options
		Write Width
		    > 1
		Read Width
			> 1
		Write Depth
			> 16384
		Read Depth
			(16384)
		Operating Mode
			> read first        <=== NOTE! ***
		Enable Port Type
			> always enabled
		> no output registers
	Port B Options
		Write Width
		    > 16
		Read Width
			> 16
		Write Depth
			(1024)
		Read Depth
			(1024)
		Operating Mode
			> write first
		Enable Port Type
			> always enabled
		> no output registers
	Other Options
	    > none
	Summary (if anything here is different you configured something incorrectly)
		#18k:1 #36k:0 A-latency:1 B-latency:1 addr-A-width:14 addr-B-width:10


Adder/Subtracter (12.0):

used by cpu.v:
    Component Name
        ipcore_add_u32b
    Basic
        Implement using
            > DSP48
        A
            Input Type
                > unsigned
            Input Width
                > 32
            Add mode
                > add
            Output Width
                > 33
            Latency Configuration
                > manual
            Latency
                > 0
        B
            Input Type
                > unsigned
            Input Width
                > 32
    Control
        Carry In
            > yes
        Carry Out
            > no
        SCLR
            > no
        Bypass
            > no

used by gps/demod.v:
    Component Name
        ipcore_add_u30b
    Basic
        Implement using
            > DSP48
        A
            Input Type
                > unsigned
            Input Width
                > 30
            Add mode
                > add
            Output Width
                > 31
            Latency Configuration
                > manual
            Latency
                > 0
        B
            Input Type
                > unsigned
            Input Width
                > 30
    Control
        Carry In
            > yes
        Carry Out
            > no
        SCLR
            > no
        Bypass
            > no

used by rx/{cic_iq_seq.v, cic_prune_seq.v}:
    Component Name
        ipcore_add_s48b
    Basic
        Implement using
            > DSP48
        A
            Input Type
                > unsigned
            Input Width
                > 32
            Add mode
                > add
            Output Width
                > 33
            Latency Configuration
                > manual
            Latency
                > 0
        B
            Input Type
                > unsigned
            Input Width
                > 32
    Control
        Carry In
            > yes
        Carry Out
            > no
        SCLR
            > no
        Bypass
            > no


Accumulator (12.0):

used by {kiwi.v, gps/demod.v}:
    Component Name
        ipcore_acc_u32b
    Basic
        Implement using
            > DSP48
        Input Type
            > unsigned
        Input Width
            > 32
        Output Width
            > 32
        Accumulation Mode
            > add
        Latency Configuration
            > manual
        Latency
            > 1
    Control
        Clock Enable
            > no
        Carry In
            > no
        SCLR
            > yes
        Bypass
            > no


DDS Compiler (6.0):

used by rx/{iq_mixer.v, gen.v}:
    Component Name
        ipcore_dds_sin_cos_13b_15b
    Configuration
        Configuration Options
            > phase generator and sin cos lut
        System Requirements
            System Clock
                > 66.6666
            Number of Channels
                > 1
            Mode of Operation
                > standard
        Parameter Selection
            > hardware parameters
        Noise Shaping
            > phase dithering
        Hardware Parameters
            Phase Width
                > 32
            Output Width
                > 15
    Implementation
        Phase Increment Programmability
            > streaming
        Resync
            > no
        Phase Offset Programmability
            > none
        Output
            Output Selection
                > sine and cosine
            Polarity
                > no
            Amplitude Mode
                > full range
        Implementation Options
            Memory Type
                > block ROM
            Optimization Goal
                > area
            DSP48 Use
                >minimal
            Has Phase Out
                > no
    Detailed Implementation
        AXI Channel Options
            DATA Has TLAST
                > not required
            Output TREADY
                > no
            TUSER Options
                Input
                    > not required
            Output Form
                > twos complement
        Latency Options
            Latency Configuration
                > auto
        Control Signals
            > none
	Summary (if anything here is different you configured something incorrectly)
        Output Width = 15 Bits
        Channels = 1
        System Clock = 66.6666 MHz
        Frequency per Channel (Fs) = 66.666600000000003 MHz
        Noise Shaping = Phase Dithering
        Memory Type = Block ROM
        Optimization Goal = Area
        Phase Width = 32 bits
        Frequency Resolution = 0.015522027388315065 Hz
        Phase Angle Width = 13 Bits
        Spurious Free Dynamic Range = 90 dB
        Latency = 8
        DSP48 slice = 0
        BRAM (18k) count = 2
